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HB52E649E12-A6B/B6B
512 MB Registered SDRAM DIMM 64-Mword x 72-bit, 100 MHz Memory Bus, 1-Bank Module (18 pcs of 64 M x 4 Components) PC100 SDRAM
E0020H20 (Ver. 2.0) Aug. 20, 2001 (K) Description
The HB52E649E12 belongs to 8-byte DIMM (Dual In-line Memory Module) family, and has been developed as an optimized main memory solution for 8-byte processor applications. The HB52E649E12 is a 64M x 72 x 1-bank Synchronous Dynamic RAM Registered Module, mounted 18 pieces of 256-Mbit SDRAM (HM5225405BTT) sealed in TSOP package, 1 piece of PLL clock driver, 2 pieces of register driver and 1 piece of serial EEPROM (2-kbit) for Presence Detect (PD). An outline of the HB52E649E12 is 168-pin socket type package (dual lead out). Therefore, the HB52E649E12 makes high density mounting possible without surface mount technology. The HB52E649E12 provides common data inputs and outputs. Decoupling capacitors are mounted beside each TSOP on the module board.
Features
* Fully compatible with : JEDEC standard outline 8-byte DIMM : Intel PCB Reference design (Rev.1.2) * 168-pin socket type package (dual lead out) Outline: 133.37 mm (Length) x 43.18 mm (Height) x 4.00 mm (Thickness) Lead pitch: 1.27 mm * 3.3 V power supply * Clock frequency: 100 MHz (max) * LVTTL interface * Data bus width: x 72 ECC * Single pulsed RAS * 4 Banks can operates simultaneously and independently * Burst read/write operation and burst read/single write operation capability * Programmable burst length: 1/2/4/8 * 2 variations of burst sequence Sequential
Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.
HB52E649E12-A6B/B6B
Interleave * Programmable CE latency : 3/4 (HB52E649E12-A6B) : 4 (HB52E649E12-B6B)
* Byte control by DQMB * Refresh cycles: 8192 refresh cycles/64 ms * 2 variations of refresh Auto refresh Self refresh
Ordering Information
Type No. HB52E649E12-A6B HB52E649E12-B6B Frequency 100 MHz 100 MHz CE latency 3/4 4 Package Contact pad 168-pin dual lead out socket type Gold
Pin Arrangement
1 pin 10 pin 11 pin
40 pin 41 pin
84 pin
85 pin 94 pin 95 pin 124 pin 125 pin
168 pin
Data Sheet E0020H20 2
HB52E649E12-A6B/B6B
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 Pin name VSS DQ0 DQ1 DQ2 DQ3 VCC DQ4 DQ5 DQ6 DQ7 DQ8 VSS DQ9 DQ10 DQ11 DQ12 DQ13 VCC DQ14 DQ15 CB0 CB1 VSS NC NC VCC W DQMB0 DQMB1 S0 NC VSS A0 A2 A4 Pin No. 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 Pin name VSS NC S2 DQMB2 DQMB3 NC VCC NC NC CB2 CB3 VSS DQ16 DQ17 DQ18 DQ19 VCC DQ20 NC NC NC VSS DQ21 DQ22 DQ23 VSS DQ24 DQ25 DQ26 DQ27 VCC DQ28 DQ29 DQ30 DQ31 Pin No. 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 Pin name VSS DQ32 DQ33 DQ34 DQ35 VCC DQ36 DQ37 DQ38 DQ39 DQ40 VSS DQ41 DQ42 DQ43 DQ44 DQ45 VCC DQ46 DQ47 CB4 CB5 VSS NC NC VCC CE DQMB4 DQMB5 NC RE VSS A1 A3 A5 Pin No. 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 Pin name VSS CKE0 NC DQMB6 DQMB7 NC VCC NC NC CB6 CB7 VSS DQ48 DQ49 DQ50 DQ51 VCC DQ52 NC NC REGE VSS DQ53 DQ54 DQ55 VSS DQ56 DQ57 DQ58 DQ59 VCC DQ60 DQ61 DQ62 DQ63
Data Sheet E0020H20 3
HB52E649E12-A6B/B6B
Pin No. 36 37 38 39 40 41 42 Pin name A6 A8 A10 (AP) BA1 VCC VCC CK0 Pin No. 78 79 80 81 82 83 84 Pin name VSS CK2 NC WP SDA SCL VCC Pin No. 120 121 122 123 124 125 126 Pin name A7 A9 BA0 A11 VCC CK1 A12 Pin No. 162 163 164 165 166 167 168 Pin name VSS CK3 NC SA0 SA1 SA2 VCC
Pin Description
Pin name A0 to A12 Function Address input Row address Column address BA0/BA1 DQ0 to DQ63 CB0 to CB7 S0, S2 RE CE W DQMB0 to DQMB7 CK0 to CK3 CKE0 WP REGE* SDA SCL SA0 to SA2 VCC VSS NC Note: 1. REGE V IH: Register mode. REGE V IL: Buffer mode.
1
A0 to A12 A0 to A9, A11
Bank select address Data input/output Check bit (Data input/output) Chip select input Row enable (RAS) input Column enable (CAS) input Write enable input Byte data mask Clock input Clock enable input Write protect for serial PD Register/Buffer enable Data input/output for serial PD Clock input for serial PD Serial address input Primary positive power supply Ground No connection
Data Sheet E0020H20 4
HB52E649E12-A6B/B6B
Serial PD Matrix*1
Byte No. Function described 0 1 2 3 4 5 6 7 8 9 Number of bytes used by module manufacturer Total SPD memory size Memory type Number of row addresses bits Number of column addresses bits Number of banks Module data width Module data width (continued) Module interface signal levels SDRAM cycle time (highest CE latency) 10 ns SDRAM access from Clock (highest CE latency) 6 ns Module configuration type Refresh rate/type Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 1 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 1 1 0 0 1 0 80 08 04 0D 0B 01 48 00 01 A0 128 256 byte SDRAM 13 11 1 72 bit 0 (+) LVTTL CL = 3
10
0
1
1
0
0
0
0
0
60
*7
11 12
0 1
0 0
0 0
0 0
0 0
0 0
1 1
0 0
02 82
ECC Normal (7.8125 s) Self refresh 64M x 4 x4 1 CLK
13 14 15
SDRAM width Error checking SDRAM width
0 0
0 0 0
0 0 0
0 0 0
0 0 0
1 1 0
0 0 0
0 0 1
04 04 01
SDRAM device attributes: 0 minimum clock delay for back-toback random column addresses SDRAM device attributes: Burst lengths supported SDRAM device attributes: number of banks on SDRAM device SDRAM device attributes: CE latency (-A6B) (-B6B) 0 0
16 17
0 0
0 0
0 0
1 0
1 1
1 0
1 0
0F 04
1, 2, 4, 8 4
18
0
0
0
0
0
1
1
0
06
2/3
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 1
0 0 0 1
1 0 0 1
0 0 0 1
0 1 1 1
04 01 01 1F
3 0 0 Registered
19 20 21
SDRAM device attributes: S latency SDRAM device attributes: W latency SDRAM device attributes
Data Sheet E0020H20 5
HB52E649E12-A6B/B6B
Byte No. Function described 22 23 SDRAM device attributes: General SDRAM cycle time (2nd highest CE latency) (-A6B) 10 ns (-B6B) Undefined 24 SDRAM access from Clock (2nd highest CE latency) (-A6B) 6 ns (-B6B) Undefined 25 SDRAM cycle time (3rd highest CE latency) Undefined SDRAM access from Clock (3rd highest CE latency) Undefined Minimum row precharge time Row active to row active min RE to CE delay min Minimum RE pulse width Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments 0 1 0 0 0 1 0 0 1 0 1 0 1 0 0 0 0E A0 VCC 10% CL = 2 *7
0 0
0 1
0 1
0 0
0 0
0 0
0 0
0 0
00 60
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
00 00
26
0
0
0
0
0
0
0
0
00
27 28 29 30 31 32 33 34 35
0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x 1 1 0 0
0 0 0 1 0 1 0 1 0 0 0 1 1 0 0 x 0 0 1 1
1 1 1 1 0 0 1 0 1 0 1 0 0 0 0 x 0 0 1 1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x 1 0 0 0
1 1 1 0 0 0 0 0 0 0 0 0 0 1 0 x 0 0 1 0
0 0 0 1 0 0 0 0 0 0 1 1 0 1 0 x 0 1 0 1
0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 x 0 0 1 0
14 14 14 32 80 20 10 20 10 00 12 23 21 07 00 xx 48 42 35 32
20 ns 20 ns 20 ns 50 ns 1 bank 512M byte 2 ns* 7 1 ns* 7 2 ns* 7 1 ns* 7 Future use Rev. 1.2A 35 33 HITACHI
Density of each bank on module 1 Address and command signal input setup time Address and command signal input hold time Data signal input setup time Data signal input hold time 0 0 0 0 0 0 0 0 0 0 x 0 0 0 0
36 to 61 Superset information 62 63 SPD data revision code Checksum for bytes 0 to 62 (-A6B) (-B6B) 64 Manufacturer's JEDEC ID code
65 to 71 Manufacturer's JEDEC ID code 72 73 74 75 76 Manufacturing location Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number
* 3 (ASCII8bit code) H B 5 2
Data Sheet E0020H20 6
HB52E649E12-A6B/B6B
Byte No. Function described 77 78 79 80 81 82 83 84 85 Manufacturer's part number Manufacturer's part number Manufacturer's part Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number (-A6B) (-B6B) 86 87 88 89 90 91 92 93 94 Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Revision code Revision code Manufacturing date Manufacturing date Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x *6 -- 0 1 -- 1 0 -- 1 0 -- 0 0 -- 0 0 -- 1 1 -- 0 1 -- 0 1 -- 64 87 *5 100 MHz CL = 2/3 1 0 0 0 1 0 0 0 1 1 0 1 0 0 0 0 0 x x 0 1 1 1 0 1 1 1 0 0 1 0 1 1 1 1 1 x x 0 1 1 1 0 1 1 0 0 0 1 0 0 0 0 1 0 x x 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 x x 1 1 1 0 1 0 0 1 0 0 1 0 0 0 0 0 0 x x 0 1 0 0 0 0 1 0 0 1 1 1 0 0 0 0 0 x x 1 0 0 1 1 1 0 1 1 0 0 0 0 0 0 0 0 x x 45 36 34 39 45 31 32 2D 41 42 36 42 20 20 20 30 20 xx xx E 6 4 9 E 1 2 -- A B 6 B (Space) (Space) (Space) Initial (Space) Year code (BCD)*4 Week code (BCD)*4
95 to 98 Assembly serial number 99 to 125 Manufacturer specific data 126 127 Intel specification frequency Intel specification CE# latency support (-A6B) (-B6B)
1
0
0
0
0
1
0
1
85
CL = 3
Notes: 1. All serial PD data are not protected. 0: Serial data, "driven Low", 1: Serial data, "driven High" These SPD are based on Intel specification (Rev.1.2A). 2. Regarding byte32 to 35, based on JEDEC Committee Ballot JC42.5-97-119. 3. Byte72 is manufacturing location code. (ex: In case of Japan, byte72 is 4AH. 4AH shows "J" on ASCII code.) 4. Regarding byte93 and 94, based on JEDEC Committee Ballot JC42.5-97-135. BCD is "Binary Coded Decimal". 5. All bits of 99 through 125 are not defined ("1" or "0"). 6. Bytes 95 through 98 are assembly serial number. 7. These specifications are defined based on component specification, not module.
Data Sheet E0020H20 7
HB52E649E12-A6B/B6B
Block Diagram
RS0 RDQMB0 DQMB CS 4 DQ0 to DQ3 N0 I/O0 to I/O3
RDQMB4 DQMB CS 4 DQ32 to DQ35 N9 I/O0 to I/O3
D0
D9
DQMB CS 4 DQ4 to DQ7 RDQMB1 DQMB CS 4 DQ8 to DQ11 N2 I/O0 to I/O3 N1 I/O0 to I/O3
DQMB CS 4 DQ36 to DQ39 RDQMB5 DQMB CS 4 DQ40 to DQ43 N11 I/O0 to I/O3 N10 I/O0 to I/O3
D1
D10
D2
D11
DQMB CS 4 DQ12 to DQ15 N3 I/O0 to I/O3
DQMB CS 4 DQ44 to DQ47 N12 I/O0 to I/O3
D3
D12
DQMB CS CB0 to CB3 RS2 RDQMB2 DQMB CS 4 DQ16 to DQ19 N5 I/O0 to I/O3 4 N4 I/O0 to I/O3
DQMB CS CB4 to CB7 4 N13 I/O0 to I/O3
D4
D13
RDQMB6 DQMB CS 4 DQ48 to DQ51 N14 I/O0 to I/O3
D5
D14
DQMB CS DQ20 to DQ23 RDQMB3 DQMB CS 4 DQ24 to DQ27 N7 I/O0 to I/O3 4 N6 I/O0 to I/O3
DQMB CS DQ52 to DQ55 RDQMB7 DQMB CS 4 DQ56 to DQ59 N16 I/O0 to I/O3 4 N15 I/O0 to I/O3
D6
D15
D7
D16
DQMB CS 4 DQ28 to DQ31 S0, S2 DQMB0 to DQMB7 BA0 to BA1 A0 to A12 RE CE CKE0 W VCC R101 REGE PLL CK R200 CK0 R201 to R203 CK1 to CK3 VCC C0 to C18 VSS C19 to C44 VSS C100 to C102 VCC (D0 to D17, U0) C200 to C201 VSS (D0 to D17, U0) PLL R E G I S T E R N8 I/O0 to I/O3
DQMB CS 4 DQ60 to DQ63 N17 I/O0 to I/O3
D8
D17
RS0, RS2 RDQMB0 to RDQMB7 RBA0 to RBA1 -> BA0 to BA1: SDRAMs D0 to D17 RA0 to RA12 -> A0 to A12: SDRAMs D0 to D17 RRAS -> RAS: SDRAMs D0 to D17 CCAS -> CAS: SDRAMs D0 to D17 RCKE0 -> CKE: SDRAMs D0 to D17 RW -> WE: SDRAMs D0 to D17
Serial PD SCL SCL SDA SDA WP A2 R100
U0
A0 A1
SA0 SA1 SA2 VSS Notes: 1. The SDA pull-up resistor is required due to the open-drain/open-collector output. 2. The SCL pull-up resistor is recommended because of the normal SCL line inacitve "high" state. * D0 to D17: HM5225405 PLL: 2509 Register: 16835 U0: EEPROM C0 to C18: 0.22 F C19 to C44: 2200 pF C100 to C102: 10pF R200 to R203: 10 R100: 47 k R101: 10 k C200 to C201: 2.2 F N0 to N17: Network registor 10
Data Sheet E0020H20 8
HB52E649E12-A6B/B6B
Absolute Maximum Ratings
Parameter Voltage on any pin relative to V SS Supply voltage relative to VSS Short circuit output current Power dissipation Operating temperature Storage temperature Note: 1. Respect to V SS Symbol VT VCC Iout PT Topr Tstg Value -0.5 to VCC + 0.5 ( 4.6 (max)) -0.5 to +4.6 50 18.0 0 to +55 -50 to +100 Unit V V mA W C C Note 1 1
DC Operating Conditions (Ta = 0 to +55C)
Parameter Supply voltage Symbol VCC VSS Input high voltage Input low voltage Notes: 1. 2. 3. 4. 5. VIH VIL Min 3.0 0 2.0 0 Max 3.6 0 VCC 0.8 Unit V V V V Notes 1, 2 3 1, 4 1, 5
All voltage referred to V SS The supply voltage with all VCC pins must be on the same level. The supply voltage with all VSS pins must be on the same level. VIH (max) = VCC + 2.0 V for pulse width 3 ns at VCC. VIL (min) = VSS - 2.0 V for pulse width 3 ns at VSS .
Data Sheet E0020H20 9
HB52E649E12-A6B/B6B
DC Characteristics (Ta = 0 to 55C, VCC = 3.3 V 0.3 V, VSS = 0 V)
HB52E649E12 -A6B Parameter Operating current (CE latency = 3) (CE latency = 4) Symbol I CC1 I CC1 Min -- -- -- -- -- -- -- Max 2220 2220 564 546 870 582 1050 -B6B Min -- -- -- -- -- -- -- Max -- 2220 564 546 870 582 1050 Unit mA mA mA mA mA mA mA CKE = VIL, t CK = 12 ns CKE = VIL, t CK = CKE, S = VIH, t CK = 12 ns CKE = VIL, t CK = 12 ns CKE, S = VIH, t CK = 12 ns t CK = min, BL = 4 I CC4 I CC4 I CC5 I CC6 I LI I LO VOH VOL -- -- -- -- -10 -10 2.4 -- 2220 2220 4470 564 10 10 -- 0.4 -- -- -- -- -10 -10 2.4 -- -- 2220 4470 564 10 10 -- 0.4 mA mA mA mA A A V V VIH VCC - 0.2 V VIL 0.2 V 0 Vin VCC 0 Vout VCC DQ = disable I OH = -4 mA I OL = 4 mA 8 6 7 4 1, 2, 6 1, 2, 4 1, 2, 5 Test conditions Burst length = 1 t RC = min Notes 1, 2, 3
Standby current in power I CC2P down Standby current in power I CC2PS down (input signal stable) Standby current in non power down Active standby current in power down Active standby current in non power down Burst operating current (CE latency = 3) (CE latency = 4) Refresh current Self refresh current Input leakage current Output leakage current Output high voltage Output low voltage I CC2N I CC3P I CC3N
Notes: 1. I CC depends on output load condition when the device is selected. ICC (max) is specified at the output open condition. 2. One bank operation. 3. Input signals are changed once per one clock. 4. Input signals are changed once per two clocks. 5. Input signals are changed once per four clocks. 6. After power down mode, CK operating current. 7. After power down mode, no CK operating current. 8. After self refresh mode set, self refresh current.
Data Sheet E0020H20 10
HB52E649E12-A6B/B6B
Capacitance (Ta = 25C, VCC = 3.3 V 0.3 V)
Parameter Input capacitance (Address) Input capacitance (RE, CE, W) Input capacitance (CKE) Input capacitance (S) Input capacitance (CK) Input capacitance (DQMB) Input/Output capacitance (DQ) Notes: 1. 2. 3. 4. Symbol CI1 CI2 CI3 CI4 CI5 CI6 CI/O1 Max 15 15 23 15 40 15 15 Unit pF pF pF pF pF pF pF Notes 1, 2, 4 1, 2, 4 1, 2, 4 1, 2, 4 1, 2, 4 1, 2, 4 1, 2, 3, 4
Capacitance measured with Boonton Meter or effective capacitance measuring method. Measurement condition: f = 1 MHz, 1.4 V bias, 200 mV swing. DQMB = VIH to disable Data-out. This parameter is sampled and not 100% tested.
AC Characteristics (Ta = 0 to 55C, VCC = 3.3 V 0.3 V, VSS = 0 V)
HB52E649E12 -A6B/B6B Parameter System clock cycle time (CE latency = 3) (CE latency = 4) CK high pulse width CK low pulse width Access time from CK (CE latency = 3) (CE latency = 4) Data-out hold time CK to Data-out low impedance CK to Data-out high impedance Data-in setup time Data in hold time Address setup time Address hold time CKE setup time CKE setup time for power down exit CKE hold time Symbol t CK t CK t CKH t CKL t AC t AC t OH t LZ t HZ t DS t DH t AS t AH t CES t CESP t CEH Tsi Thi Tsi Thi Tsi Tpde Thi PC100 Symbol Tclk Tclk Tch Tcl Tac Tac Toh Min 10 10 4 4 -- -- 2.1 1.1 -- 2.9 1.9 2.6 1.6 2.6 2.6 1.6 Max -- -- -- -- 6.9 6.9 -- -- 6.9 -- -- -- -- -- -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 1, 2 1, 2, 3 1, 4 1 1 1 1, 5 1, 5 1 1 1 1 1, 2 Notes 1
Data Sheet E0020H20 11
HB52E649E12-A6B/B6B
AC Characteristics (Ta = 0 to 55C, VCC = 3.3 V 0.3 V, VSS = 0 V) (cont)
HB52E649E12 -A6B/B6B Parameter Command setup time Command hold time Symbol t CS t CH PC100 Symbol Tsi Thi Trc Tras Trcd Trp Tdpl Trrd Min 2.6 1.6 70 50 20 20 10 20 1 -- Max -- -- -- 120000 -- -- -- -- 5 64 Unit ns ns ns ns ns ns ns ns ns ms Notes 1 1 1 1 1 1 1 1
Ref/Active to Ref/Active command period t RC Active to precharge command period Active command to column command (same bank) Precharge to active command period Write recovery or data-in to precharge lead time Active (a) to Active (b) command period Transition time (rise to fall) Refresh period Notes: 1. 2. 3. 4. 5. t RAS t RCD t RP t DPL t RRD tT t REF
AC measurement assumes t T = 1 ns. Reference level for timing of input signals is 1.5 V. Access time is measured at 1.5 V. Load condition is C L = 50 pF. t LZ (min) defines the time at which the outputs achieves the low impedance state. t HZ (max) defines the time at which the outputs achieves the high impedance state. t CES defines CKE setup time to CK rising edge except power down exit command.
Test Conditions * Input and output timing reference levels: 1.5 V * Input waveform and output load: See following figures
2.4 V
input
0.4 V
2.0 V 0.8 V
DQ CL t
T
tT
Data Sheet E0020H20 12
HB52E649E12-A6B/B6B
Relationship Between Frequency and Minimum Latency
Parameter Frequency (MHz) tCK (ns) Active command to column command (same bank) Active command to active command (same bank) Active command to precharge command (same bank) Precharge command to active command (same bank) Write recovery or data-in to precharge command (same bank) Active command to active command (different bank) Self refresh exit time Last data in to active command (Auto precharge, same bank) Self refresh exit to command input Precharge command to high impedance (CE latency = 3) (CE latency = 4) Last data out to active command (auto precharge) (same bank) Last data out to precharge (early precharge) (CE latency = 3) (CE latency = 4) Column command to column command Write command to data in latency DQMB to data in DQMB to data out CKE to CK disable Register set to active command S to command disable Power down exit to command input HB52E649E12 -A6B/B6B PC100 Symbol Symbol 10 I RCD I RC I RAS I RP I DPL I RRD I SREX I APW I SEC Tsrx Tdal Tdpl 2 7 5 2 1 2 2 3 7 Notes 1 = [IRAS + IRP] 1 1 1 1 1 2 = [IDPL + IRP] = [IRC] 3
I HZP I HZP I APR I EP I EP I CCD I WCD I DID I DOD I CLE I RSA I CDD I PEC
Troh Troh
3 4 0 -2 -3
Tccd Tdwd Tdqm Tdqz Tcke Tmrd
1 1 1 3 2 1 0 1
Notes: 1. I RCD to IRRD are recommended value. 2. Be valid [DESL] or [NOP] at next command of self refresh exit. 3. Except [DESL] and [NOP]
Data Sheet E0020H20 13
HB52E649E12-A6B/B6B
Pin Functions
CK0 to CK3 (input pin): CK is the master clock input to this pin. The other input signals are referred at CK rising edge. S0, S2 (input pin): When S is Low, the command input cycle becomes valid. When S is High, all inputs are ignored. However, internal operations (bank active, burst operations, etc.) are held. RE, CE and W (input pins): Although these pin names are the same as those of conventional DRAMs, they function in a different way. These pins define operation commands (read, write, etc.) depending on the combination of their voltage levels. For details, refer to the command operation section. A0 to A12 (input pins): Row address (AX0 to AX12) is determined by A0 to A12 level at the bank active command cycle CK rising edge. Column address (AY0 to AY9, AY11) is determined by A0 to A9, A11 level at the read or write command cycle CK rising edge. And this column address becomes burst access start address. A10 defines the precharge mode. When A10 = High at the precharge command cycle, all banks are precharged. But when A10 = Low at the precharge command cycle, only the bank that is selected by BA0/BA1 (BA) is precharged. BA0/BA1 (input pin): BA0/BA1 are bank select signal (BA). The memory array is divided into bank 0, bank 1, bank 2 and bank 3. If BA0 is Low and BA1 is Low, bank 0 is selected. If BA0 is High and BA1 is Low, bank 1 is selected. If BA0 is Low and BA1 is High, bank 2 is selected. If BA0 is High and BA1 is High, bank 3 is selected. CKE0 (input pin): This pin determines whether or not the next CK is valid. If CKE is High, the next CK rising edge is valid. If CKE is Low, the next CK rising edge is invalid. This pin is used for power-down and clock suspend modes. DQMB0 to DQMB7 (input pins): Read operation: If DQMB is High, the output buffer becomes High-Z. If the DQMB is Low, the output buffer becomes Low-Z. Write operation: If DQMB is High, the previous data is held (the new data is not written). If DQMB is Low, the data is written. DQ0 to DQ63, CB0 to CB7 (input/output pins): Data is input to and output from these pins. VCC (power supply pins): 3.3 V is applied. VSS (power supply pins): Ground is connected.
Detailed Operation Part
Refer to the HM5225165B/HM5225805B/HM5225405B-75/A6/B6 datasheet (E0082H).
Data Sheet E0020H20 14
HB52E649E12-A6B/B6B
Physical Outline
Front side 0.60 133.37 + 0.15 - (75.113) (DATUM -A-) (63.67) (29.119) 3.00 0.10 4.00 max.
Unit: mm
3.00 typ
Component area (Front)
1 11.43 C 36.83 133.37 0.15 B 54.61 A 84
1.27 0.10
Back side 2 - 3.00 0.10
127.35 0.15
4.00 0.10
17.80 0.70 Detail C (DATUM -A-) 1.00 6.35 2.00 0.10 3.125 0.125
Component area (Back)
(DATUM -A-) Detail A 2.50 0.20 1.27 0.20 0.15 Detail B R FULL
R FULL
6.35 4.175 2.00 0.10
1.00 0.05
Note: Tolerance on all dimensions 0.15 unless otherwise specified.
Data Sheet E0020H20 15
3.125 0.125
38.964 1.534 43.18 1.70
4.00 min 168
85
HB52E649E12-A6B/B6B
Cautions
1. Elpida Memory, Inc. neither warrants nor grants licenses of any rights of Elpida Memory, Inc.'s or any third party's patent, copyright, trademark, or other intellectual property rights for information contained in this document. Elpida Memory, Inc. bears no responsibility for problems that may arise with third party's rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability. However, contact Elpida Memory, Inc. before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. Design your application so that the product is used within the ranges guaranteed by Elpida Memory, Inc. particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Elpida Memory, Inc. bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Elpida Memory, Inc. product does not cause bodily injury, fire or other consequential damage due to operation of the Elpida Memory, Inc. product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Elpida Memory, Inc.. 7. Contact Elpida Memory, Inc. for any questions regarding this document or Elpida Memory, Inc. semiconductor products.
Data Sheet E0020H20 16

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